Thin wafer detectors with improved radiation damage and crosstalk characteristics

ABSTRACT

The present invention is directed toward a detector structure, detector arrays, and a method of detecting incident radiation. The present invention comprises several embodiments that provide for reduced radiation damage susceptibility, decreased affects of crosstalk, reduced dark current (current leakage) and increased flexibility in application. In one embodiment, a photodiode array comprises a substrate having at least a front side and a back side, a plurality of diode elements integrally formed in the substrate forming the array, wherein each diode element has a p+ fishbone pattern on the front side, and wherein the p+ fishbone pattern substantially reduces capacitance and crosstalk between adjacent photodiodes, a plurality of front surface cathode and anode contacts, and wire interconnects between diode elements made through a plurality of back surface contacts.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/081,366, filed on Mar. 16, 2004, which relies on, for priority, U.S.patent application Ser. No. 10/838,897 having a filing date of May 5,2004, entitled “THIN WAFER DETECTORS WITH IMPROVED RADIATION ANDCROSSTALK CHARACTERISTICS” which further relies on ProvisionalApplication 60/468,181, having a priority date of May 5, 2003, entitled“DETECTORS WITH IMPROVED RADIATION DAMAGE AND CROSSTALKCHARACTERISTICS”.

FIELD OF THE INVENTION

The present invention pertains generally to the field of radiationdetectors, and in particular, relates to radiation detectorsmanufactured with a fishbone structure to reduce both capacitance andcrosstalk between detecting regions.

BACKGROUND OF THE INVENTION

Arrays of photosensitive diodes are used in an assortment ofapplications including, but not limited to, radiation detection, opticalposition encoding, and low light-level imaging, such as nightphotography, nuclear medical imaging, photon medical imaging,multi-slice computer tomography (CT) imaging, and ballistic photondetection etc. Typically, photodiode arrays may be formed as one- ortwo-dimensional arrays of aligned photodiodes, or, for optical shaftencoders, a circular or semicircular arrangement of diodes.

One problem with detection devices is that they are susceptible tovarious radiation damage mechanisms, such as displacement damageresulting in total dose effects and ionization damage resulting in bulkeffects. Both these mechanisms adversely affect the performance ofdetectors, transistors and integrated circuits.

Certain detector characteristics that are most affected include detectorleakage current, doping characteristics, charge collection, and carrierlifetime. Over time, detectors show an increased reverse-bias currentand decreased forward voltage due to radiation damage. Further, a changein doping level, due to radiation damage, adversely affects the width ofthe depletion region, i.e. the voltage required for full depletion and adecrease in carrier lifetime results in signal loss as carriersrecombine while traversing the depletion region.

Another disadvantage with conventional detection devices is the amountand extent of crosstalk that occurs between adjacent detectorstructures, primarily as a result of minority carrier leakage currentbetween diodes. The problem of crosstalk between diodes becomes evenmore acute as the size of the detector arrays, the size of individualdetectors, the spatial resolution, and spacing of the diodes is reduced.

In certain applications, it is desirable to produce optical detectorshaving small lateral dimensions and spaced closely together. For examplein certain medical applications, it would beneficial to increase theoptical resolution of a detector array in order to permit for improvedimage scans, such as computer tomography scans. However, at conventionaldoping levels utilized for diode arrays of this type, the diffusionlength of minority carriers generated by photon interaction in thesemiconductor is in the range of at least many tens of microns, and suchminority carriers have the potential to affect signals at diodes awayfrom the region at which the minority carriers were generated.Therefore, the spatial resolution obtainable may be limited by diffusionof the carriers within the semiconductor itself, even if othercomponents of the optical system are optimized and scattered light isreduced.

The conduction process in semiconductor devices is accomplished via twotypes of current flow: hole current and electron current. Morespecifically, energy can be added to electrons via external sources ofenergy, such as light and heat. When excess energy is absorbed byvalence electrons, covalent bonds may be broken. Once the bonds arebroken, the electrons move to the conduction band where they are capableof supporting electric current. When a voltage is applied to a crystalsubstance containing the conduction band electrons, the electrons movethrough the crystal toward the applied voltage, thus creating electroncurrent flow.

In contrast, a hole results when a covalent bond is broken and a vacancyis left in the atom by the missing valence electron. The hole has apositive charge because its corresponding atom is deficient by oneelectron. As a result of this positive charge, a chain reaction beginswhen a nearby electron breaks its covalent bond to fill the hole, thusleaving another hole in an adjacent atom. This process continues,resulting in a covalent bond in the atom with the original hole and aresulting hole in the adjacent atom. Although the electron has movedfrom one covalent bond to another, the hole is also moving throughadjacent or nearby atoms. Thus, since this conduction process resultsfrom the movement of holes rather than electrons, it is referred to ashole flow (hole current flow or conduction by holes).

Hole flow is similar to electron flow, except that the holes move towarda negative potential and in an opposite direction to that of theelectrons. For example, electrons flow from negative to positivepotential, whereas hole flow moves from a positive to negativepotential. Majority carriers are the more abundant charge carriers,while less abundant carriers are referred to as minority carriers. In ann-type semiconductor material, electrons are the majority carriers andholes are the minority carriers. In a p-type semiconductor material, theopposite is true, thus holes are the majority carriers and electrons arethe minority carriers. Since hole flow results from the breaking ofcovalent bonds at the valence band level, the electrons associated withthis conduction must remain in the valence band. In contrast, electronsassociated with electron flow, however, have conduction band energy andcan move throughout the crystal.

Drift current is charged particle motion in response to an appliedelectric field. When an electric field is applied across asemiconductor, the carriers start moving, thus producing a current. Thepositively charged holes move with the electric field while thenegatively charged electrons move against the electric field. The motionof each carrier is referred to as constant drift velocity, or v_(d),taking into consideration the collisions and setbacks each carrier haswhile in transit. Note that the sum total of the carriers willeventually travel in the direction they are supposed to regardless ofany setbacks or collisions.

The drift current is thus the result of carrier drift, and depends uponthe ability of the carriers to move around, or electron and holemobility. The carrier concentration is another parameter that affectsdrift current, simply because carriers have to be present for there tobe current. Yet another parameter that is measured with drift current,is the current density, which depends upon the electric field, electronor hole concentration (−/+q), the mobility constant, and the charge.Note than when a negative electric field is applied, the electrons (−q)will travel opposite the electric field, thus the resulting driftcurrent will be positive.

Diffusion is the process of particles dispersing from regions of highconcentration to regions of low concentration. If this process is leftundisturbed, there will eventually be a uniform distribution ofparticles. Diffusion does not require external forces to act upon agroup of particles. The particles move about using thermal motion. Ifthe particles are carriers, they “carry” charge with them, thusresulting in current, and therefore diffusion current. Diffusion currentwill occur even when there is no electric field applied to thesemiconductor. D_(p), and D_(n) are called the diffusion coefficients, aproportionality factor. In addition, the direction of the diffusioncurrent depends on the change in the carrier concentrations, not theconcentrations themselves. Usually +q is assigned to holes whereas −q toelectrons, because the carriers are diffusing from areas of highconcentrations to areas of low concentrations.

Drift current and diffusion current comprise the total current in asemiconductor, although they may not be occurring simultaneously. Underequilibrium conditions, the current density should be zero because noelectric field is applied. If the doping is not completely uniform,however, there will be a change in concentration in some places in thesemiconductor, resulting in a gradient. This gradient may give rise toan electric field, which in turn can result in non-zero currentdensities.

As mentioned above, in order for current to exist, electrons and holesmust move and transport charge, or exhibit mobility. Several factors canaffect the mobility of a carrier, the most significant of which isscattering, or the motion-impending collisions within the crystal. Thesecollisions can occur with an electron bumping into another electron, ahole, or even ionized impurities. Scattering may increase or decrease,depending upon factors such as temperature and/or the addition ofelectron acceptors/donors. In general, the higher the temperature, themore excited the carriers are, and therefore the greater the increase inscattering. The same phenomenon occurs with dopants, as not only willthere be more carriers to bump into and scatter, but dopants willgenerate an ionized impurity that will also carry a charge. Mobility issubstantially independent of the doping concentration when the dopingconcentration is low. The mobility of the carriers begins to decrease asthe concentration of the dopant increases.

Various approaches have been used to minimize such crosstalk including,but not limited to, providing inactive photodiodes to balance theleakage current, as described in U.S. Pat. Nos. 4,904,861 and 4,998,013to Epstein et al., the utilization of suction diodes for the removal ofthe slow diffusion currents to reduce the settling time of detectors toacceptable levels, as described in U.S. Pat. No. 5,408,122, andproviding a gradient in doping density in the epitaxial layer, asdescribed in U.S. Pat. No. 5,430,321 to Effelsberg.

Despite attempts to improve the overall performance characteristics ofphotodiode arrays and their individual diode units, within detectionsystems, photodiode arrays capable of reducing crosstalk while beingless susceptible to radiation damage are still needed. Additionally,there is need for a semiconductor circuit and an economically feasibledesign and fabrication method so that it is capable of improving thespatial resolution of detectors integrated therein.

SUMMARY OF THE INVENTION

The present invention is directed toward a detector structure, detectorarrays, and a method of detecting incident radiation. The presentinvention comprises several embodiments that provide for reducedradiation damage susceptibility, decreased affects of crosstalk, reduceddark current (current leakage) and increased flexibility in application.

In one embodiment, the present invention comprises a back sideilluminated photodiode array with front side contacts that minimizes thedepletion region, thereby decreasing the affects of crosstalk. Thefabrication of the array involves diffusing a n+ layer on the back sideof the substrate, forming a deep n+ region; applying a first maskinglayer on the back side; applying a second masking layer on the backside; applying a photoresist mask on the back side, forming an etchingpattern; using the etching pattern to etch the first masking layer, thesecond masking layer; removing the photoresist mask; etching the deep n+region, and the substrate; and finally coating the back side of thesubstrate with an antireflective coating.

In one embodiment, the photodiode array comprises a substrate having atleast a front side and a back side, a plurality of photodiodesintegrally formed in the substrate forming the array, a plurality ofmetal contacts provided on the front side, wherein the fabrication ofsaid array comprises (1) coating the front side of the substrate withSiO₂ via mask oxidation, (2) masking the front side of the substratewafer with n+, (3) etching an oxide pattern on the front side of thesubstrate wafer and etching the back side of the substrate wafer withoxide, (4) diffusing a n+ layer on the front side of the substrateforming a deep n+ region, (5) applying a p+ layer on the front side ofthe substrate, forming an etching pattern; (6) selectively etching thefront side of the substrate according to the p+ etch pattern, (7)diffusing a p+ layer on the substrate wafer, (8) applying a photoresistlayer on the front side of the substrate, (9) applying an oxide layer onthe back side of the substrate, (10) diffusing a shallow n+ layer on theback side of the substrate, (11) coating the back side of the substratewith an antireflective layer, (12) etching a contact window oxide on thefront side of the substrate, (13) removing the contact window oxideafter the etching step, and (14) metallizing, masking, and etching thefront side of the substrate.

Optionally, the substrate is made of n doped silicon. The siliconsubstrate has a thickness ranging from 0.075 mm to 0.275 mm. Theplurality of n+ and p+-doped regions are separated from a substantiallyuniform n+ layer by and active region. The p+ mask pattern is a narrowfishbone pattern. The narrow fishbone pattern p+ mask comprises p+ bonesand is defined by a periphery frame bone. The gap between the p+ bonesin said narrow fishbone pattern is preferably in a range of 100 μm to180 μm.

Optionally, the gap between the p+ periphery frame bone and a top n+cathode on the substrate is 25 μm. The gap between the p+ peripheryframe bone and a top n+ cathode on the substrate is 50 μm. The gapbetween the p+ periphery frame bone and a top n+ cathode on thesubstrate is 75 μm. The heavily doped diffusion regions are heavilydoped pad layers of a selected conductivity type of either p+ doped orn+ doped.

Optionally, the antireflective coating layer is a thin film material.The thin film material is one of an oxide, a sulfide, a fluoride, anitride, a selenide, or a metal. The antireflective coating is a silicondioxide antireflective.

In one embodiment, a photodiode array comprises a substrate having atleast a front side and a back side, a plurality of diode elementsintegrally formed in the substrate forming the array, wherein each diodeelement has a p+ fishbone pattern on the front side, and wherein the p+fishbone pattern substantially reduces capacitance and crosstalk betweenadjacent photodiodes, a plurality of front surface cathode and anodecontacts, and wire interconnects between diode elements made through aplurality of back surface contacts.

Optionally, the array further comprises a plurality of top cathode pads.The photodiode array comprises four top cathode pads. Each of the fourtop cathode pads is common to and located in the center of four diodeelements. The four diode elements are located in each of four corners ofsaid photodiode array. At least one anode pad is located in the centerof each diode element.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features and advantages of the present invention will beappreciated, as they become better understood by reference to thefollowing detailed description when considered in connection with theaccompanying drawings:

FIG. 1 a is a cross sectional view of one front side of one embodimentof a back side etched, front side contact photodiode array of thepresent invention;

FIG. 1 b is a cross sectional view of one embodiment of a back sideetched, front side contact photodiode array of the present invention,also illustrating a front side of the present invention;

FIG. 2 a is cross sectional view of an embodiment of the back side of aback side etched, front side contact photodiode array of the presentinvention;

FIG. 2 b is a cross sectional view of one embodiment of the back side ofa back side etched, front side contact photodiode array of the presentinvention;

FIG. 3 depicts a back side illuminated, front side contact photodiodearray of the present invention, further comprising a handle wafer, forimproved strength and manageability;

FIG. 4 a depicts a back side illuminated, front side contact photodiodearray of the present invention, further comprising a handle wafer;

FIG. 4 b depicts a back side illuminated, front side contact photodiodearray of the present invention, further comprising a handle wafer; and

FIGS. 5 a, 5 b, and 5 c depict different views of an array ofphotodiodes with a plurality of trenches functioning as isolationtrenches, to non-conductively isolate electrically active regions fromeach other; and

FIG. 6 depicts a portion of a conventional three-dimensional (3-D)photodiode array with a p+ fishbone structure;

FIGS. 7 a, 7 b, and 7 c, illustrate the photodiode arrays of the presentinvention, having p+ fishbone structures on the front side, wherein thegap between the bones is respectively smaller than of those shown inFIG. 6;

FIG. 8 a depicts a top view of the photodiode array of the presentinvention;

FIG. 8 b depicts an enlarged view of a portion of the photodiode arrayof the present invention, demarcated as portion “A” with a dotted circlein FIG. 8 a; and

FIGS. 9 a-9 g illustrate steps in a manufacturing process of thephotodiode array of the present invention, in which p+ fishbone maskingis employed.

DESCRIPTION OF THE INVENTION

This application hereby incorporates by reference co-pending applicationSer. No. 10/797,324, entitled “FRONT ILLUMINATED BACK SIDE CONTACT THINWAFER DETECTORS”, which also relies on, for priority, U.S. ProvisionalApplication 60/468,181, having a priority date of May 5, 2003, entitled“DETECTORS WITH IMPROVED RADIATION DAMAGE AND CROSSTALKCHARACTERISTICS”. The invention described therein comprises a pluralityof front side illuminated photodiodes, optionally organized in the formof an array, with both the anode and cathode contact pads on the backside. The front side illuminated, back side contact (FSL-BSC)photodiodes have superior performance characteristics, including lessradiation damage, less crosstalk using a suction diode, and reliance onreasonably thin wafers.

At least one invention described therein is a photodiode array having asubstrate with at least a front side and a back side; a plurality ofphotodiodes integrally formed in the substrate forming the array whereineach photodiode has a middle layer juxtaposed between a front layer anda back layer; a plurality of electrical contacts in electricalcommunication with the back side; and suction diodes positioned atselected locations within the array, wherein the fabrication of saidarray involves a masking process comprising the steps of applying afirst p+ mask on said front side and applying a second p+ mask on saidback side.

The present invention is directed toward a detector structure, detectorarrays, and a method of detecting incident radiation. Variousmodifications to the embodiments will be readily apparent to those ofordinary skill in the art, and the disclosure set forth herein may beapplicable to other embodiments and applications without departing fromthe spirit and scope of the present invention and the claims heretoappended. Thus, the present invention is not intended to be limited tothe embodiments described, but is to be accorded the broadest scopeconsistent with the disclosure set forth herein.

The present invention comprises several embodiments that provide forreduced radiation damage susceptibility, decreased affects of crosstalk,and increased flexibility in application. In one embodiment, the presentinvention comprises a back side illuminated photodiode array with a backside etching that minimizes the active area layer, thereby decreasingthe affects of crosstalk. The back side etching is preferably, but by noway of limitation, in the form of “U” or “V” shaped grooves. The backside illuminated with back side etching (BSL-BE) photodiodes areimplemented in an array and have superior performance characteristics,including less radiation damage due to a thinner active area, and lesscrosstalk due to shorter distances for minority carriers to diffuse tothe PN junction.

Referring now to FIGS. 1 a, 1 b, 2 a, and 2 b, the active areas in theback side of the photodiode arrays are etched to minimize the likelihoodof crosstalk while still providing the detector with sufficient strengthto avoid easy breakage. FIGS. 1 a, 1 b, 2 a, and 2 b depict exemplaryphotodiode arrays having a first region of maximum thickness, a secondregion of minimum thickness, and a third region of varying thicknesswhich depends upon the level of back side etching. The “regions” areloosely defined areas of the photodiode arrays and are described hereinto illustrate the teachings of the present invention. While theseregions are present in the embodiments as described in theabove-mentioned figures, the specifications regarding the number ofregions and their corresponding thicknesses that comprise the photodiodearray are merely illustrative of the present invention and not intendedto be limiting.

The first region comprises p+ regions and n+ regions that are separatedby a thin active layer, minimizing the degree of crosstalk between thediodes and reducing susceptibility to radiation damage. The secondregion comprises a shallow n+ region and, optionally, a deep n+ region,both doped with a suitable impurity of a similar conductivity type andlocated close to the back side of the wafer. The second region providesthe photodiode area with increased strength and resistance to breakage.The third region forms the bottom surface wall (depth) of preferably “U”or “V” shaped grooves etched into the back side of the photodiode arrayand spans to the front side surface of the device wafer. Ideally, thetotal depth of the first region would equal the total depth of thesecond and third regions combined.

In one embodiment, the back side illuminated photodiode arrays of thepresent invention have front side contacts. Referring now to FIG. 1 a,an embodiment of the front side of the photodiode arrays of the presentinvention is depicted. Metal contact pads are provided on the front andare in electrical communication with the anode and cathode surfacestructures. Both regions 150 a and 155 a are positioned directly belowthe front surface of the device wafer 105 a, sharing their top face withfront surface of device wafer 105 a. Heavily doped regions 150 a and 155a may be doped with a suitable impurity of a selected conductivity type,such as p-type or n-type. Regions 150 a and 155 a are doped withopposite impurities of selected conductivities. For example, but notlimited to such example, if region 150 a is doped with a suitableimpurity of selected conductivity that is p-type, then region 155 a isdoped with n-type. In addition, a thin region of active layer separatesregions 150 a and 155 a. The thin active layer minimizes the degree ofcross talk between diodes and reduces susceptibility to radiationdamage.

Referring again to FIG. 1 a, cross section 105 a of one embodiment ofphotodiode array 100 a is shown. Photodiode array 100 a comprisesregions, including first region 110 a, second region 115 a and thirdregion 120 a, with maximum, minimum, and variable thicknesses,respectively. As an example, and by no way of limitation, the threeregions may possess the following specifications: first region 110 a mayhave a thickness of approximately 125 μm, second region 115 a may have athickness of approximately 50 μm, and third region 120 a may be of avarying thickness, ranging from a minimum of approximately 75 μm to amaximum of approximately 125 μm, depending on the level and pattern ofetching. The above-mentioned specifications are only mentioned by way ofillustration and are not binding. The specification can be easilychanged to suit the design, fabrication, and functional requirementssuggested herein.

First region 110 a comprises two heavily doped regions, 150 a and 155 a,as described above. First region 110 a is separated into two additionalregions for ease of discussion—second region 115 a and third region 120a. Second region 115 a, in one embodiment, comprises shallow n+ regions135 a and deep n+ regions 130 a, both doped with a suitable impurity ofa similar conductivity type and located close to the back side of thewafer. Both shallow n+ regions 135 a and deep n+ regions 130 a mayoptionally be heavily doped with an impurity of similarly selectedconductivity type, such as p-type or n-type. A large active area fillsthe depth created at the junction of both shallow n+ region 135 a anddeep n+ region 130 a. For example, and by no way of limitation, shallown+ region 135 a is preferably 0.3 μm in thickness and deep n+ region 130a is preferably 2 μm in thickness. Second region 115 a provides thephotodiode array with increased strength and resistance to breakage.Third region 120 a, in combination with second region 115 a, forms “U”or “V” shaped etchings in the back side of photodiode (depending on thetype of etching used).

Referring now to FIG. 2 a, a cross sectional view of one embodiment of asingle crystal semiconductor substrate or device wafer 201 a having aplurality of photodiodes positioned in an array 200 a therein isdepicted. Note that the front side of photodiode array 200 a is asdepicted and described above with reference to FIG. 1 a. Device wafer201 a comprises three regions, including first region 215 a, secondregion 220 a, and third region 230 a, with maximum, minimum, andvariable thicknesses, respectively. Various constructional details withrespect to the regions in photodiode array 200 a have been explainedwith reference to FIG. 1 a above and will not be discussed here. Generaldimensions and relevant specifications, however, are discussed in thefollowing paragraph and are by no way limiting to the design of thisembodiment of the present invention.

Referring back to FIG. 2 a, first region 215 a is preferably of athickness of approximately 125 μm and further comprises a p+ region andan n+ region, separated by a thin active layer just below the front sideof device wafer 201 a. Second region 220 a preferably has a minimumthickness 50 μm and preferably comprises a shallow n+ region 202 a and adeep n+ region 203 a, both doped with a suitable impurity of a similarconductivity type. Shallow n+ region 202 a is preferably 0.3 μm inthickness and deep n+ region 203 a is preferably 2 μm in thickness—bothlocated close to the back side of device wafer 201 a. Deep n+ region 203a serves to reduce dark leakage current in the photodiode array.

Device wafer 201 a may be made up of various materials, and ispreferably, but not limited to Si or Ge. The crystal orientation ofwafer 201 a is preferably <1-0-0>. The back side of device wafer 201 ais selectively etched, at appropriate positions via a suitable etchingtechnique to form three dimensional (hereinafter, “3-D”) microstructurestherein, thus minimizing the active area layer and decreasing theaffects of crosstalk. The grooves are preferably “U” or “V” shaped witha depth of approximately 50 μm from the back surface. The presentinvention may employ various other 3-D microstructures of varying shapesand dimensions including, but not limited to, grooves, pyramidal pits,pyramidal cavities etc. for minimizing active area layers. Such variousother microstructures will be readily apparent to one of ordinary skillin the art having the benefit of this disclosure. The abovespecifications are not limiting with respect to the 3-D microstructuresand their accompanying dimensions can be changed to suit any design,fabrication, and functional requirements.

For example, and by no way of limitation, a wet etching technique isused to form concave “V”-shaped grooves on the back side of device wafer201 a, at suitable positions, such as positions 205 a, as shown in FIG.2 a. Via such wet etch technique, mono-crystalline wafers etch faster incertain crystallographic directions than in others, thereby allowing forcertain layers or portions of the wafer to act as a “stop” for the etchprocess. This involves both a selection of appropriate wafer orientationand a suitable mask pattern for the photographic mask. Optionally,reactive ion etching (RIE) may be used to form concave grooves on theback side of device wafer 201 a. The grooves formed via this technique,however, form “U”-shaped grooves. The sidewalls of such grooves are morevertical, wherein the wall is angled at less than 10 degrees.

As shown in FIG. 2 a, portions of the back side of photodiode array 200a comprise three layers, forming dielectric membrane 255 a. Three-layerdielectric membrane 255 a forms a bridge between V-shaped grooves 235 a.First layer 270 a is comprised of SiO₂ and is preferably of a thicknessof 4000 Å. Si₃N₄ comprises second layer 275 a and is preferably of athickness of 2000 Å. Third layer 280 a of dielectric membrane 255 a iscomprised of SiO₂, as an antireflective coating, and is preferably of athickness of 900 Å. A person of ordinary skill would appreciate that thespecifications and dimensions of the components of the dielectricmembrane are not limited to the abovementioned specifications and can beeasily adjusted to suit varied economical, technical or operationalspecifications.

“V”-shaped grooves 235 a etched into device wafer 201 a form bottoms 240a, created at a depth 245 a of the “V”-shaped groove from the backsideof device wafer 201 a. Sidewalls 250 a extend from bottom 240 a to theback side of device wafer 201 a, at an angle. Preferably, “V”-shapedgrooves 235 a are of a depth of approximately 50 μm (depicted as 245 a)and are located at a distance of approximately 75 μm from the front sideof wafer 201 a. A person of ordinary skill would appreciate that thespecifications and dimensions of the “V”-shaped grooves etched into thewafer are not limited to the abovementioned specifications and can beeasily adjusted to suit varied economical, technical or operationalspecifications.

As a first manufacturing step, back side of device wafer 201 a isheavily doped via phosphorus diffusion or high dose implantation,followed by deep driving, thus obtaining a deep n+ doped region 203 a.Subsequent to the formation of the deep n+ doped region, back side ofdevice wafer 201 a is first coated with first layer 270 a of a suitablemasking material. Preferably, first masking layer 270 a is fabricatedfrom a material such as SiO₂ and in a thickness of 4000 Å. Back side ofdevice wafer 201 a is then coated with second layer 275 a, comprisingSi₃N₄, and preferably of a thickness of 2000 Å. A person of ordinaryskill in the art would appreciate that the utilization of materials forthe fabrication of first and second masking layers are not limited toSiO₂ or Si₃N₄, and can easily be changed to suit other design oroperational requirements.

Once first layer 270 a and second layer 275 a are applied to back sideof device wafer 201 a, the back side is coated with a conventionalphotoresist mask, thus forming a window pattern on the back side ofwafer 201 a. The photoresist mask is formed using any of theconventional photolithographic techniques including, but not limited to,optical, UV (i.e. ultraviolet), EUV (i.e. enhanced ultraviolet)photolithography, e-beam or ion-beam lithography, x-ray lithography,interference lithography, or any other similar technique. Second layer275 a is then etched in accordance with the formed window pattern, usinga dry etching (gas) process. First layer 270 a acts as a stop etch layerin the dry etch process, as the process passes through SiO₂ at asignificantly slower rate than Si₃N₄. First layer 270 a is then etchedaccording to the window pattern via the use of buffered HF₂, therebyexposing device wafer 201 a, coated with deep n+ regions 203 a throughthe pattern achieved via the use of the photoresist mask. Thephotoresist mask is then removed from the back side of the wafer, priorto etching the grooves in the substrate, as the wet etchant would damagethe photoresist mask. As an alternative, the Si₃N₄ layer and patternalready formed in the previous steps functions as the etch mask.

“V”-shaped grooves are then etched into device wafer 201 a and deep n+regions 203 a, through the use of a wet (chemical) etch process. It ispreferable to use KOH in the chemical etch process of this step. It mustbe noted here that the etch rate of the silicon wafer is orientationdependent—the more slowly etched crystal planes form the side and endwalls of the V-grooves. Device wafer 201 a is preferably a wafer havinga crystal orientation <1-0-0>. V-shaped grooves etched parallel to the<1-1-0>direction have planar facets which bind the V-shaped grooves,lying in the <1-1-1>plane. The planar facets are inclined at an angle of54.7° with respect to the <1-0-0>plane. The groove sizes are controlledby the corresponding mask windows, the accuracy of their alignment withthe crystal axes, the erosion rate of the edges of the mask, and therelative etch rates of the crystal planes. Typically, the finishedwidths of V-grooves can be controlled to within 0.5 to 1 μm.Manufacturing methods of 3-D microstructures, such as concave cavitiesor grooves, of various shapes and textures in semiconductor substratesare well known in the art. Orientation selective wet etching techniquesincluding, but not limited to, isotropic, anisotropic etching, etc. arepreferred. Like other conventional etching techniques, orientationselective wet etching techniques also utilize custom-made orconventional mask patterns. Preferably, a “V”-shaped groove pattern,formed on a suitable photographic mask in accordance with the principlesof the present invention, is used to protect one area of the wafer 201 aduring the stripping and etching processes. The present invention,however, is directed towards providing methods of masking and etchingthe active area, thereby used to minimize the likelihood of crosstalkwhile still providing the detector with sufficient strength to avoideasy breakage. The scope and spirit of the invention is no way limited,and other 3-D microstructures may be etched into the back side of wafersin accordance to the properties of the present invention.

After “V”-shaped grooves are etched into the device wafer shallow n+layer 202 a is diffused onto the back side of device wafer 201 a. Theback side of device wafer 201 a, including the surface of V-shapedgrooves 235 a, is then coated with layer 280 a, an antireflectivecoating. Various antireflective coating designs, such as 1 layer, 2layer, 3 layer, and 4+ layers may be employed. By way of example, and byno means limiting, the 1-layer antireflective coating design adoptedherein utilizes thin film materials, such as oxides, sulfides,fluorides, nitrides, selenides, metals, among others. In one embodimentof the present invention, layer 280 a comprises SiO₂ AR (i.e. silicondioxide antireflective). Preferably, the SiO₂ AR layer has a thicknessof 900 Å.

Referring now to FIG. 2 b, the back side of another embodiment of thepresent invention is depicted. Note that the front side of photodiodearray 200 b has already been described above with respect to FIG. 1 a.Device wafer 201 b comprises three regions, including first region 215b, second region 220 b, and third region 230 b, with maximum, minimum,and variable thicknesses, respectively. By way of comparison with FIG. 2a, FIG. 2 b depicts a cross section of photodiode array 200 b withoutdeep n+ region (shown as 203 a in FIG. 2 a). Third region 230 b is of avarying thickness and in combination with second region 220 b,constitutes “U”-shaped or “V”-shaped etchings 235 b in the back side ofwafer 201 b. Various constructional details with respect to the threeregions in photodiode array 200 b have been explained with reference toFIGS. 1 a and 2 a and will not be discussed here. It should be noted,however, that the first manufacturing step as described with respect toFIG. 2 a is omitted in the manufacture of photodiode array 200 b due tothe omission of the deep n+ region.

Now, referring back to FIG. 1 a, the back side of yet another embodimentof the back side of the photodiode array of the present invention isdepicted. Note that front side characteristics and optimal dimensionswith respect to FIG. 1 a have already been discussed above. Device wafer105 a may be made up of various materials, and is preferably, but notlimited to Si or Ge. The crystal orientation of wafer 105 a ispreferably <1-0-0>. Back side of device wafer 105 a is selectivelyetched, at appropriate positions via a suitable etching technique toform three dimensional (hereinafter, “3-D”) microstructures therein,thus minimizing the active area layer and decreasing the affects ofcrosstalk. The grooves are preferably “U” or “V” shaped with a depth ofapproximately 50 μm from the back surface. The present invention mayemploy various other 3-D microstructures of varying shapes anddimensions including, but not limited to, grooves, pyramidal pits,pyramidal cavities etc. for minimizing active area layers. Such variousother microstructures will be readily apparent to one of ordinary skillin the art having the benefit of this disclosure. The abovespecifications are not limiting with respect to the 3-D microstructuresand their accompanying dimensions can be changed to suit any design,fabrication, and functional requirements.

For example, and by no way of limitation, a wet etching technique isused to form “V” shaped grooves on the back side of device wafer 105 a,at suitable positions, such as positions 125 a, as shown in FIG. 1 a.Via such wet etch technique, monocrystalline wafers etch faster incertain crystallographic directions than in others, thereby allowing forcertain portions of the wafer to act as a “stop” for the etch process.This involves both a selection of appropriate wafer orientation and asuitable mask pattern for the photographic mask. Optionally, reactiveion etching (RIE) may be used to form concave grooves on the back sideof device wafer 105 a. The grooves formed via this technique, however,form “U”-shaped grooves. The sidewalls of such grooves are morevertical, wherein the wall is angled at less than 10 degrees.

As a first manufacturing step, back side of device wafer 105 a isheavily doped via phosphorus diffusion or high dose implantation,followed by deep driving to obtain a deep n+ doped region 130 a. Firstlayer 140 a, of a suitable masking material, is then thermally grownonto the back side of device wafer 105 a. Preferably, the first maskinglayer is fabricated from a material such as SiO₂ and in a thickness of4700 Å. Back side of device wafer 105 a is then coated with second layer165 a, comprising deposited Si₃N₄, and preferably of a thickness of 2000Å. A person of ordinary skill in the art would appreciate that theutilization of materials for the fabrication of first and second maskinglayers are not limited to SiO₂ or Si₃N₄, and can easily be changed tosuit other requirements.

Once first layer 140 a and second layer 165 a are applied to back sideof device wafer 105 a, the back side is coated with a conventionalphotoresist mask, thus forming a window etch pattern. The photoresistmask is formed using any of the conventional photolithographictechniques including, but not limited to, optical, UV (i.e.ultraviolet), EUV (i.e. enhanced ultraviolet) photolithography, e-beamor ion-beam lithography, x-ray lithography, interference lithography, orany other similar technique. Second layer 165 a is then etched inaccordance with the formed window pattern, using a dry etching (gas)process. First layer 140 a acts as a stop etch layer in the dry etchprocess, as the process passes through SiO₂ at a significantly slowerrate than Si₃N₄. First layer 140 a is then etched in the window patternvia the use of buffered HF₃, thereby exposing device wafer 105 a anddeep n+ regions 130 a through the window pattern achieved via the use ofthe photoresist mask.

The photoresist mask is then removed from the back side of the wafer,prior to etching the grooves in the substrate, as the wet etchant woulddamage the photoresist mask. As an alternative, the Si₃N₄ layer andpattern already formed in the previous steps functions as the etch mask.

“V”-shaped grooves 170 a are then etched into device wafer 105 a, firstremoving doped n+ deep regions 130 a. After “V”-shaped grooves areetched into the device wafer shallow n+ layer 135 a is diffused onto theback side of device wafer 105 a, coating only the surface of V-shapedgrooves 170 a. The surface of V-shaped grooves 170 a is then coated withlayer 145 a, an antireflective coating. Various antireflective coatingdesigns, such as 1 layer, 2 layer, 3 layer, and 4+ layers may beemployed. By way of example, and by no means limiting, the 1-layerantireflective coating design adopted herein utilizes thin filmmaterials, such as oxides, sulfides, fluorides, nitrides, selenides,metals, among others. In one embodiment of the present invention, layer145 a comprises SiO₂ AR (i.e. silicon dioxide antireflective).Preferably, the SiO₂ AR layer has a thickness of 900 Å.

Referring now to FIG. 1 b, a second embodiment of a photodiode array 100b is depicted. Photodiode array 100 b comprises first region 110 b,second region 115 b, and third region 120 b, dimensional details ofwhich are discussed above with reference to FIG. 1 a. In addition, thedoping materials used, masking layers formed, and etching techniquesadopted to form the 3-D microstructures have already been explainedabove with reference to FIG. 1 a. In the manufacture of photodiode array100 b, however, only a single first masking layer is applied to the backside of the photodiode array. For example, and by no way of limitation,the single masking layer 165 b is preferably Si₃N₄ and of a thickness of4000 Å. In addition, second region 115 b comprises only a shallow n+region 135 b.

Referring to FIG. 3, another embodiment of the photodiode array of thepresent invention is illustrated. The back side illuminated, front sidecontact (BSL-FSC) photodiodes are implemented in an array and havesuperior performance characteristics, including low dark current(current leakage), very high shunt resistance, less crosstalk, and lessradiation damage due to a thinner active area. To improve strength andmanageability, the photodiode as shown in FIG. 3 further comprises ahandle wafer. The front surface cathode and anode contacts are broughtto the surface of the handle wafer through the metallization of channelsconnecting a p+ metal pad to the p+ region and an n+ metal pad to the n+region. The starting material for photodiode array 300 is device wafer301 with handle wafer 302 bonded to the front surface of device wafer301.

Handle wafer 302 has channels 303 a, 303 b, and 303 c (hereinafterreferred to collectively as “303”) formed in handle wafer 302 at threepositions, for example and by no means limiting, those marked “A”, “B”,and “C”. Starting precisely from the top surface of handle wafer 302,channels 303 extend through the total depth of handle wafer 302 to thefront side of the device wafer 301. The side walls of the handle wafer302 define channels 303. Handle wafer 302 is coated with a first layer304 and a second layer 305, both forming top and sidewalls of handlewafer 302. First oxide insulation layer 304 coats the inner walls ofchannels 303. For example, but not limited to such example, SiO₂ may beused for the first oxide insulation layer 304. Second layer 305, layeredon top of first layer 304, coats a major portion of the inner wallsforming channels 303 and at least partially covering the top surface ofhandle wafer 302. Second layer 305, a heavily doped pad layer of aselected conductivity type, in conjunction with layer 304 coats innerwalls which form channels 303. Preferably, second layer 305 is either p+doped or n+ doped. Second layer 305 in channel 303 at area “B” uses a n+doped pad wherein p+ doped pads are used at areas “A” and “C”.

Channels 303, having first layer 304 and second layer 305 coating sidewalls of handle wafer 302 and forming inner walls of channel 303, arevertically aligned with respect to layers 306, 308, and 309. Furthersecond layer 305 (vertical p+ pad in this embodiment) in channels 303comprising areas “A” and “C” covers a large portion, preferably asubstantial portion of the depth of channel 303 (or the portion thatsubstantially forms the depth of handle wafer 302). Bottom layers 306and 308 are in electrical communication with horizontal p+ pads 307 asdepicted in the cross-sectional view of FIG. 3. In channel 303comprising area “B”, horizontal n+ pad 307 is electrically connected ton+ region 309.

Areas between second layers 305 (either p+ or n+), running along thesidewalls of handle wafer 302 and forming channels 303, can be describedas void areas “A”, “B”, and “C”. Due to metallization of channels 303along the entire periphery of the vertical sidewall layer 305 and thehorizontal pads 307 therein, the front surface cathode and anodecontacts on device wafer 301 are brought to the surface of the handlewafer 302 with channels 303 connecting the p+ metal pads to the p+regions and the n+ metal pads to the n+ regions.

The back side of device wafer 301, as shown in FIG. 3, has already beendescribed in one embodiment with respect to FIG. 2 a. The description asoffered in FIG. 2 a is herein incorporated by reference.

Various other methods of physically separating active regions ofphotodiode arrays may be readily apparent to a person of ordinary skillin the art. It should be noted that the above description aboutseparation of active regions of individual photodiodes, via formation ofinsulation layers there between, is merely for illustrative purposes andnot intended to limit the applicability of the present invention.

Referring now to FIGS. 4 a and 4 b, additional embodiments of the backside illuminated-front side contact photodiode arrays are shown. TheBSL-FSC photodiodes have thin active layers, thereby improving crosstalkcharacteristics and reducing susceptibility to radiation damage. Aplurality of p+ and n+ regions are separated by a shallow active region.To improve strength and manageability, the photodiode further comprisesa handle wafer. The front surface cathode and anode contacts are broughtto the surface of the handle wafer through the metallization of channelsconnecting a p+ metal pad to the p+ region and an n+ metal pad to the n+region.

Referring now to FIG. 4 a, a cross sectional view of one embodiment ofthe present invention is shown. As an example, and by no way oflimitation, silicon may be utilized in accordance with the principles ofthe present invention. The starting material for the BSL-FSC photodiodeis a silicon wafer comprising a device wafer 401 a bonded to a handlewafer 402 a using a suitable bonding material via an appropriate methodof bonding silicon wafers. Such bonding methods are well known to one ofordinary skill in the art. Both device wafer 401 a and handle wafer 402a are preferably formed of the same semiconductor material of a selectedconductivity type, such as p-type or n-type. The device wafer 401 apreferably has a thickness of approximately 50 μm.

Handle wafer 402 a increases strength in the BSL-FSC photodiode whileimproving manageability. The front surface cathode and anode contactsare brought to the top surface of the handle wafer 402 a through themetallization of channels 404 a connecting a p+ pad to the p+ region anda n+ pad to the n+ region. Channels 404 a, formed in handle wafer 402 aare marked with area designations “A”, “B”, and “C”. The inner sidewalls of handle wafer 402 forming channels 404 a comprise first layer405 a, which is an oxide insulation layer and second layer 406 a, whichis a contact layer for handle wafer 402 a. Material selection andmanufacturing method for such layers have already been described withreference to FIG. 3 and will not be described in detail here.

As shown in FIG. 4 a, boron doped polysilicon is preferably used as thematerial for second layer 406 a, and define defining channel areas “A”and “C”, in conjunction with first layer 405 a and bottom wall 407 a. Aperson of ordinary skill in the art would readily appreciate that theselection and utilization of material for the second sidewall layer isnot limited to boron doped polysilicon and can be changed to suit variedtechnical and operational specifications. Second sidewall layer 406 adefining channel area “B” preferably comprises, but is not limited tophosphorus doped polysilicon.

Also depicted in FIG. 4 a is a plurality of selected p+ and n+ dopedregions separated from a substantially uniform shallow n+ layer 403 a bya thin active region. Portions of the thin active region or layer arealso juxtaposed between the plurality of p+ and n+ regions. The shallown+ layer 403 a improves the quantum efficiency at shorter wavelengthsand reduces dark current (current leakage) of the photodiode.

Referring now to FIG. 4 b, a cross sectional view 400 b of anotherembodiment of the BSL-FSC photodiode is shown. The specifications of theBSL-FSC photodiode are described above with respect to cross section 400a of FIG. 4 a. In contrast, however, FIG. 4 b employs p+ metal padlayers and n+ metal pad layers as the sidewalls that define channels 401b. FIG. 4 b shows front surface cathode and anode contacts, brought tothe surface of handle wafer 402 b through the metallization of channels401 b connecting a p+ metal pad to the p+ region and an n+ metal pad tothe n+ region.

In another embodiment, the present invention comprises a front sideilluminated photodiode array with zero crosstalk due to dielectricisolation. The front side illuminated, zero crosstalk (BSL-ZC)photodiodes are implemented in an array and have superior performancecharacteristics, including less radiation damage due to a thinner activearea and zero crosstalk due to a complete isolation of the carrierregions. FIGS. 5 a, 5 b, and 5 c depict different views of an array ofphotodiodes with a plurality of trenches functioning as isolationtrenches, to non-conductively isolate electrically active regions fromeach other.

Specifically, FIG. 5 a depicts one such exemplary trench, functioning asan isolation trench. A device layer 515 is in physical communicationwith a trench defined by a doped trench sidewall 530, a trench sidewallliner 535, preferably an oxide, and polysilicon 540 as a filler. Thetrench is further defined by a polysilicon step 520, preferably having aheight at or around 300 nm, and a TEOS trench endpoint 525, preferablyhaving a height at or around 500 nm. In one embodiment, the trench has awidth at or around 2.5 μm to 4 mu. In the abovementioned embodiment,various specifications for device wafer thicknesses and trench widthsare provided. The provided specifications are not limiting with respectto device wafer thicknesses and trench widths and their accompanyingdimensions can be changed to suit any design, fabrication, andfunctional requirements.

Trench sidewall 530 is of n-type (phosphorous) doping, if the devicelayer material is also n-type. The doping type of the trench sidewalllayer matches that of the device layer. Sheet resistance of the trenchsidewall doping is less than 50 ohm per square. The trench sidewallliner thickness, for each sidewall, is 150 nm+/−35 nm. The polysilicon540 filled trench isolated photodiode array 500 eliminates electricalmigration between the adjacent detecting regions therein, therebypreventing minority carrier leakage current and achieving zero crosstalkcharacteristics.

Custom silicon-on-insulator (SOI) starting material for photodiode array500 of the present invention is a device layer 515 with a buried layer505 formed on top of a buried oxide (BOX) layer, resting on a handlewafer 503. Handle wafer 503 can be of any type as is well known to thoseof ordinary skill in the art, ranging from handle wafers of lowresistivity to handle wafers of high resistivity. Additionally, low costhandle wafers may be employed. Also, handle wafers of optimalperformance can be used. Handle wafer 503 is doped with an impurity of aselected conductivity type, either n-type or p-type and preferably has athickness of approximately 300-700 μm.

Handle wafer 503 is oxidized, thereby forming a buried oxide layersurrounding the handle wafer. Device layer 515 is preferably adouble-sided polished wafer (to improve bonding characteristics) and issubjected to shallow n+ diffusion or ion implantation, thereby forminglayer 505 on the back side of device layer 515. The front side of handlewafer 503, covered with the oxide layer, is then bonded to the backsideof device layer 515, which has an original thickness of 400 μm. The BOXlayer is used for the bonding process.

Device layer 515 is preferably formed of the same semiconductor materialas handle wafer 503 and is ground and polished to a thickness of 20 μm.It is ground and polished to such desired thickness. Optionally, devicelayer 515 may be grown as an epitaxial layer on top of handle wafer 503.The positioning of the trenches is then formed using a standardphotolithography step, as mentioned above, thereby obtaining a patternon the thinned wafer. Using the photoresist pattern, a dry etchingtechnique, such as reactive ion etching is then used to etch the siliconwafer for trench formation. The photoresist layer is removed followingthe step of silicon trench etching.

Trench sidewall 530 is deposited via, but not limited to, a thermaldeposition technique. The sidewall oxide layer 535 is then formed alongthe vertical wall of the trench. The wafers are then subjected topolysilicon deposition, thereby filling the trenches with polysilicon.It is preferred that the trenches in this embodiment of the presentinvention are filled after the growth of trench sidewall liner 535, sothat the polysilicon 540 filler is more likely to be void free. In thefinal step, a TEOS oxide layer is deposited on the surface.

Referring now to FIGS. 5 b and 5 c, an array of photodiodes affixed to ahandle wafer 503 with a layer of buried oxide therebetween is shown.Note that photodiode array 500 is front side illuminated because thepresence of the buried oxide layer will act as an impenetrable barrierto a light generated carrier. Each photodiode has surface n+ and surfacep+ regions separated from a base n+ region by an active layer and areseparated from adjacent photodiodes by a trench acting as an isolatinglayer. Spaced semiconductor regions 545 are formed in device layer 515via standard semiconductor processing, masking and etching techniques,as are well known to those of ordinary skill in the art. A boundarybetween the device layer wafer 515 and each spaced region 545 defines ap-n junction (not shown).

Of particular advantage, the present invention provides a method forfilling an isolation trench or other semiconductor structure whoseactive areas require a non-conductive material, typically but notlimited to undoped SiO₂, to physically and non-conductively isolate saidelectrically active regions.

FIG. 6 depicts a portion of a conventional three-dimensional (3-D)photodiode array 600 with a p+ fishbone structure. While the fishbonedesign structure allows for low capacitance (typically 7 pF at lowvoltage), the resultant crosstalk is high because a) the gap between thetwo adjacent bones is wide and b) there is no periphery frame bone. Ascan be seen in FIG. 6, some of the carriers generated near the edge ofthe backside of the photodiode can stray to the adjacent pixel and getcollected there, thus creating crosstalk. Photodiode array 600 comprisesa plurality of photodiode elements.

Now referring to FIG. 6, exemplary left and right diode elements 601 aand 601 b, respectively, are described in further detail. The topsurface of photodiode array 600 comprises several layers, includingfirst layer 602, second layer 603, and third layer 604. It should benoted that the corresponding layers exist in each diode element ofphotodiode array 600 but will only be described with respect to diodeelement 601 a hereinafter. From a design standpoint the dimensions ofthe silicon wafer, the number of diode elements forming the matrixarray, the number of regions, and the number of regions comprising thephotodiode array may vary and are merely illustrative of a conventionalphotodiode array.

First layer 602 is a diffused region and is heavily doped with asuitable impurity or dopant of a selected conductivity type, such asp-type or n-type. Preferably, but not limited to such example, diffusedlayer 602 is heavily doped with a suitable impurity of n-typeconductivity. An appropriate n+ dopant is employed for the n+ diffusionprocess, and includes a suitable source, such as a gas, liquid, orsolid. Many approaches for carrying out the diffusion process are wellknown to those of skill in the art and the intricacies of suchapproaches will not be discussed in detail here. The choice of diffusionmethod is dependent on various factors, such as the diffusioncoefficient of the dopant, permissible error in diffusion depth, anddiffusion source.

Second layer 603 is a diffused region and is heavily doped with asuitable impurity or dopant of a selected conductivity type, such asp-type or n-type. Preferably, but not limited to such example, diffusedlayer 603 is heavily doped with a suitable impurity of p-typeconductivity. An appropriate p+ dopant is employed for the p+ diffusionprocess, and includes a suitable source, such as a gas, liquid, orsolid. Many approaches for carrying out the diffusion process are wellknown to those of skill in the art and the intricacies of suchapproaches will not be discussed in detail here.

The choice of diffusion method is dependent on various factors, such asthe diffusion coefficient of the dopant, permissible error in diffusiondepth, and diffusion source. For example, and not limited to suchexample, the p+ dopant employed herein is boron (i.e. B) in accordancewith the principles of the present invention. P+ diffused layer 603serves as an area where the photodiode junction is active and canconvert photons thereby generating current.

The p+ fishbone mask is preferably applied to the front side the wafer,as described in further detail with the manufacturing steps below.Briefly, the front side of the wafer is preferably first coated with aSiO₂ layer and subsequently subjected to selective etching, using the p+fishbone mask to ensure certain regions retain the SiO₂ layer whileothers remain devoid of it.

Third region 604 comprises an appropriate metal. For example, but notlimited to such example, in high density packaging, as with thephotodiode array of the present invention, a metal system such as, butnot limited to Al/Ni/Au, Ni/Cr/Au, or Ti/Pd/Ag. Other metal systems maybe employed as well. In other cases, such as when the anodes andcathodes are connected to PCB/ceramic substrate via wire bonding,aluminum can be used as metallization traces and pads.

While the conventional photodiode array with a p+ fishbone structuredescribed above with respect to FIG. 6 allows for low capacitance, theresultant crosstalk is high. As can be seen in FIG. 6, some of thecarriers generated near the edge of the backside of the photodiode canstray to the adjacent pixel and get collected there, thus resulting incrosstalk.

In one embodiment, as shown in FIGS. 7-9, the present invention isdirected towards a front-side contact back side illuminated (FSC-BSL)photodiode with a special fishbone structure to reduce both capacitanceand crosstalk. Unlike conventional devices, the present inventiondiscloses both the use of a narrower gap between adjacent bones and aperiphery frame bone. Typically, carriers that are photo-generatedfurther from the p-n junction can diffuse to the p+ diffused “bones” andbe collected by the depletion region. Thus, conventional fishbonestructures can be employed when devices are made on a substantially highminority carrier lifetime silicon material. In addition, in anembodiment of the present invention, cathode and anode contacts are onthe front side of the wafer.

In an embodiment of the present invention, as described in furtherdetail with respect to FIGS. 7 a, 7 b, and 7 c, the p+ fishbone has thefollowing variable characteristics, assuming an x-y-z axis as drawn nearphotodiode 700 wherein the x-axis represents the length of the wafer,the y-axis represents the width of the wafer, and the z-axis representsthe height of the wafer: p+ to n+ separation in the x-direction, 705 a,705 b, 705 c; p+ to n+ separation in a y-direction 706 a, 706 b, 706 c;the width between two contiguous p+ fishbone ribs 707 a, 707 b, 707 c,also in the y-direction; and wafer height 708 a, 708 b, 708 c in thez-direction.

The photodiode array of the present invention, as shown in FIGS. 7 a, 7b, and 7 c, are p+ fishbone structure photodiodes wherein the gapbetween the p+ bones is preferably in a range of 100 μm to 180 μm, thusimproving the probability that the carriers will get collected by thedepletion region of at least one of the bones. In addition, there is aperiphery frame bone; thus, carriers generated near the edge on thebackside will more likely be collected by the depletion region of theframe bone. The effects of crosstalk are reduced since fewer carriersare collected by the fishbone of the adjacent diode element. The gapsbetween the p+ frame and the top n+ cathode are shown as 25 μm in FIG. 7a, 50 μm in FIGS. 7 b, and 75 μm in FIG. 7 c. The smaller the gap(between p+ and n+), the lower the crosstalk at the expense ofcapacitance and wafer processing yield.

In one embodiment, as shown in FIG. 7 a, photodiode array 700 a may havethe following variable characteristics, assuming an x-y-z axis as drawnnear photodiode 700 a wherein the x-axis represents the length of thewafer, the y-axis represents the width of the wafer, and the z-axisrepresents the height of the wafer: p+ to n+ separation 705 a in thex-direction of 0.025 mm; p+ to n+ separation 706 a in a y-direction of0.025 mm; the width between two contiguous p+ fishbone ribs 707 a, alsoin a y-direction, of 0.109 mm; and wafer height 708 a in a z-directionof approximately 0.125 mm. Also shown in FIG. 7 a is periphery framebone 709 a, which surrounds the fishbone rib structure.

In a second embodiment, as shown in FIG. 7 b, photodiode array 700 b mayhave the following variable characteristics, assuming an x-y-z axis asdrawn near photodiode 700 b wherein the x-axis represents the length ofthe wafer, the y-axis represents the width of the wafer, and the z-axisrepresents the height of the wafer: p+ to n+ separation 705 b in thex-direction of 0.050 mm; p+ to n+ separation 706 b in a y-direction of0.050 mm; the width between two contiguous p+ fishbone ribs 707 b, alsoin a y-direction, of 0.109 mm; and wafer height 708 b in a z-directionof approximately 0.125 mm. Also shown in FIG. 7 b is periphery framebone 709 b, which surrounds the fishbone rib structure.

In a third embodiment, as shown in FIG. 7 c, photodiode array 700 c mayhave the following variable characteristics, assuming an x-y-z axis asdrawn near photodiode 700 c wherein the x-axis represents the length ofthe wafer, the y-axis represents the width of the wafer, and the z-axisrepresents the height of the wafer: p+ to n+ separation 705 c in thex-direction of 0.075 mm; p+ to n+ separation 706 c in a y-direction of0.075 mm; the width between two contiguous p+ fishbone ribs 707 c, alsoin a y-direction, of 0.109 mm; and wafer height 708 c in a z-directionof approximately 0.125 mm. Also shown in FIG. 7 c is periphery framebone 709 c, which surrounds the fishbone rib structure.

FIG. 8 a depicts a top view of the photodiode array 800 of the presentinvention. Each square box represents diode elements 802 withinphotodiode array 800. In one embodiment, photodiode array 800 isarranged in the form of a 16 by 16 matrix with a total of 256 diodeelements 802 on a silicon wafer starting material (not visible anddescribed in greater detail below with reference to manufacturingprocess). Although an array of 256 diode elements 802 is illustrated inFIG. 8 a, it is to be understood that an array or matrix of diodeelements falling within the scope of the present invention may have anynumber of diode elements. A person of ordinary skill in the art wouldappreciate that the number of photodiodes incorporated in the siliconwafer is not limited to the abovementioned number and can be adjusted tosuit varied operational specifications.

The determination and/or selection of proper active area specificationsinclude, but are not limited to, geometry; dimensions; response speed;quantum efficiency at the wavelength of interest; response linearity;spatial uniformity of response; and dark noise or other noise sourcesthat impact photodiode sensitivity of the active area. In addition, thelight sensing properties and specification of the photodiodes, such as,but not limited to, sensitivity, are largely related to the size anddimensions of the active area, not its shape or geometry. For example,the leakage current of the photodiode is proportional to its activearea.

Within photodiode array 800, active areas 808 of diode elements 802provide surfaces onto which light impinges. Active areas 808 may bedesigned and fabricated using standard technology. For example, and byno way of limitation, active area photolithography may be employed todesign and fabricate active areas 808 possessing specifications inconformity of the principles of the present invention. In general,active area specifications, such as but not limited to size, shape andgeometry may vary and are determined in accordance with the principlesof the present invention. Generally, the size of the active area alsohas an effect on the linearity of the responsivity of a photodiode.Comparative studies involving photodiodes reveal that linearity isbetter in photodiodes having relatively small rather than large activeareas.

In general, conventional detectors have either round or square-shapedactive area geometry. There is no shape restriction, however, and manyapplications may require, but are not limited to triangular, radial, ortrapezoidal active areas. Since photodiodes are typically manufacturedvia standard wafer fabrication techniques involving methods of maskingand photoetching, a unique geometry depending on the requirements andspecifications is relatively simple to create. The geometry size andshape can be held to a tolerance of 2 microns.

A majority of conventional, modern, semi-conducting chips include adense array of narrow, thin-film metallic conductors, more commonlyreferred to as interconnects, that serve to transport current betweenthe various devices on the chip. As integrated circuits increase incomplexity, the individual components that comprise the integratedcircuits must become increasingly more reliable. Due to theminiaturization of very large-scale integrated circuits, however,thin-film metallic interconnects are subject to increasingly highcurrent densities. Under these conditions, electro-migration can lead toelectrical failure of interconnects in relatively short lifetimes, thusreducing the current lifetime to an unacceptable level.Electro-migration is the result of momentum transfer from electrons,which move in the applied electric field, to the ions which make up thelattice of the interconnect material. Thus, it is also of greatimportance to control electro-migration failure in thin-filminterconnects. Because thin-film interconnects in integrated circuitsare deposited onto large efficient single crystal silicon heat sinks,they can sustain current densities up to 1010 A/cm² without immediatedamage.

In narrow interconnects, electro-migration presents several differentsources of failure. The two most common are void failures along thelength of the line (called internal failures) and diffusivedisplacements at the terminals of the line that destroy electricalcontacts. Both of these failures have been attributed to themicrostructure of the line and can thus be delayed or overcome bymetallurgical changes that alter the microstructure.

Now referring back to FIG. 8 a, wire interconnects 810 (not shown)between diode elements 802 are made through back surface contacts (notshown) located in approximate vertical alignment with central areas.Wire interconnects 810 are made at the back of photodiode array 800 andare preferably minimized. Wire interconnects 810 are also made availablefor creating electrical connections with external circuits, such asprinted circuit boards (PCBs) and other devices.

Each of the four corners of the photodiode array 800 on the siliconwafer (not visibly shown, but understood to be the base of thephotodiode array) comprises a set of four diode elements 802 and acommon top cathode pad 807. FIG. 8 b depicts an enlarged view of aportion of photodiode array 800, demarcated as portion “A” in FIG. 8 aand outlined with a circle. In the enlarged view, as shown in FIG. 8 b,an exemplary corner of the photodiode array 800 is shown, with fourdiode elements 802, top cathode pad 807 in the center of the fourphotodiode elements 802, and anode metal pad 809 in the center of eachphotodiode element 802. Although only four top cathode pads 807 in a16×16 matrix photodiode array are shown it is understood that a typicalarray may have additional top cathode pads at a plurality of positionsin various other arrangements, other than those detailed herein. Centraltop cathode rings create N+N high-low junctions, and thus assist in thereduction of cross talk between individual diode elements 802.

Typically, photodiode arrays may be formed as one- or two-dimensionalarrays of aligned photodiodes, or, for optical shaft encoders, asemicircular arrangement of diodes. In similar situations, wherepossible arrangements of photodiodes include, but are not limited to,one-dimensional, circular, and semicircular types, the total number ofcentral top cathode elements may vary depending upon design parameters.

Now referring to FIGS. 9 a-9 g, a manufacturing process 900 of thephotodiode array of the present invention is described. In an embodimentof the manufacturing process of the above-described photodiode array ofthe present invention, a p+ fishbone mask is applied on the front sideof the device wafer. A plurality of n+ and p+-doped regions areseparated from a substantially uniform n+ layer by an active region.

The starting material for the back side illuminated, front-side contactphotodiode (BSL-FSC) is a device wafer 902 preferably comprised ofsilicon. In one embodiment, the silicon device wafer 902 preferably hasa thickness ranging from 0.075 mm to 0.275 mm. Device wafer 902 may bemade up of various materials, such as, but not limited, to silicon orgermanium. The crystal orientation of wafer 902 is preferably <1-0-0>.The front side of the silicon wafer is coated with a SiO₂ layer andsubjected to selective etching, utilizing the p+ fishbone mask to ensurecertain regions retain the SiO₂ layer while others remain devoid of it.

A photographic mask having the desired fishbone pattern, as describedwith reference to FIGS. 7 a, 7 b, and 7 c above, but not limited to suchconfigurations is produced. In general, photomasks are high precisionplates containing microscopic images of electronic circuits.Conventionally, they are formed from flat pieces of quartz or glass withan etched layer of chrome on one side. The etched chrome comprises aportion of the electronic circuit design and is also referred to as thegeometry of the mask. In addition, fishbone patterns or grids have atightly coupled architecture, thus facilitating a better geometry for asensor array. The dies are arranged in rows and columns on the mask.

Appropriate patterns and masking techniques may be employed inaccordance with the principles of the present invention withoutdeparting from the spirit and scope of the invention and are not limitedto the examples describe herein.

In step 905, as shown in FIG. 9 a, an n-type silicon wafer 900 issubjected to mask oxidation. Typically, the mask oxidation step isachieved via thermal oxidation of the starting silicon wafer substrate.

As shown in FIG. 9 b, in step 910, the substrate wafer 900 is thensubjected to n+ top side masking. An oxide pattern is etched on thefront side of the wafer. The front side of the wafer is then subjectedto n+ diffusion. The n+ drive-in oxidation is thus accomplished. Thefront side of the device wafer is heavily doped via phosphorus diffusionor high dose implantation, followed by deep driving, thus obtaining arelatively deep n+ diffused region 911.

In step 915, as shown in FIG. 9 c, the front side of the wafer issubjected to p+ photolithography, etching, and p+ diffusion and drive-inoxidation, resulting in p+ diffused layer 916. Thus, the backsideilluminated photodiode arrays of the present invention have front sidecontacts. Metal contact pads are provided on the front and are inelectrical communication with the anode and cathode metal structures.The n+ and p+ doped regions, shown as 911 and 916 in FIGS. 9 b and 9 c,respectively, are positioned directly below the front surface of thedevice wafer. Thus, regions 911 and 916 share their top face with frontsurface of the device wafer 902. Heavily doped regions 911 and 916 maybe doped with a suitable impurity of a selected conductivity type, suchas p-type or n-type, as described above. Diffusion regions 911 and 916are preferably doped with opposite impurities of selectedconductivities. For example, but not limited to such example, if region911 is doped with suitable impurity of a selected conductivity ofn-type, then region 916 would be doped with a suitable impurity of aselected conductivity of p-type.

As shown in FIG. 9 d, in step 920, the front side of the wafer is coatedwith a photoresist while an oxide layer is etched on the back side. Thephotoresist mask on the front side forms a contact window pattern. Thephotoresist mask is formed using any of the conventionalphotolithographic techniques including, but not limited to, optical, UV(i.e. ultraviolet), EUV (i.e. enhanced ultraviolet) photolithography,e-beam or ion-beam lithography, x-ray lithography, interferencelithography, or any other similar technique.

In step 925, as shown in FIG. 9 e, a shallow n+ layer 927 is diffused onthe back side. The n+ layer on the back side of the wafer improves thequantum efficiency at shorter wavelengths and reduces dark current(current leakage) of the photodiode. Smaller surface area portions ofthe active region are exposed via the fishbone masking pattern.

The back side is then subjected, in step 926 to thermal oxidation togrow the anti-reflective (AR) layer 928. Various anti-reflective coatingdesigns, such as 1 layer, 2 layer, 3 layer, and 4+ layers may beemployed. By way of example, and by no means limiting, the 1-layeranti-reflective coating design adopted herein utilizes thin filmmaterials, such as oxides, sulfides, fluorides, nitrides, selenides,metals, among others. In one embodiment of the present invention, theantireflective layer 928 comprises SiO₂ AR (i.e. silicon dioxideantireflective). Preferably the SiO₂ AR 928 layer has a thickness of 900Å.

As shown in FIG. 9 f, in step 930, a contact etch mask is used to etch acontact window into the front side of the wafer. The contact window isformed on the front side of the treated substrate wafer by usingstandard semiconductor technology photolithography techniques. Thecontact window oxide can then be removed by either standard wet orstandard dry etching techniques as are well known to those of ordinaryskill in the art.

Finally, in step 935, as shown in FIG. 9 g, the front side of the wafersubstrate is subjected to metallization, metal masking, andsubsequently, metal etching. Due to metallization of the area, the frontside cathode contacts 936 and front side anode contacts 937 on devicewafer 902 are on the front surface of the silicon device wafer 902 (notshown).

Various modifications to the embodiments, disclosed herein, will bereadily apparent to those of ordinary skill in the art and thedisclosure set forth herein may be applicable to other embodiments andapplications without departing from the spirit and scope of the presentinvention and the claims hereto appended. A person of ordinary skill inthe art would appreciate that the novel aspects of the present inventioncan be implemented in various designs and methods. Thus, the presentinvention is not intended to be limited to the embodiments described,but is to be accorded the broadest scope consistent with the disclosureset forth herein.

The above discussion is aimed towards providing an embodimentincorporating the novel aspects of the present invention and it shouldbe understood that the foregoing illustration is not the onlyapplication where the present invention can be reduced down to practice.The present invention can be suitably modified to incorporate otherpossible embodiments as well. The scope of the invention is definedsolely by the accompanying claims and within the scope of the claims;the present invention can be employed in various other situations. Forexample, other device-to-device isolation, active are patterning, activearea reduction, reduction of crosstalk, formation of electrical contactsvia through holes, and reduction of radiation damage techniques could beemployed while still staying within the scope of the present invention.

1-20. (canceled)
 21. A diode element, having a center, comprising: asubstrate having a front side and a back side; at least two metal lineson said front side, wherein each of said metal lines has a first end anda second end; a contiguous metallic interconnect, distinct from the atleast two metal lines, wherein said contiguous metallic interconnectencircles said metal lines and is in physical communication with atleast one of the first end or second end of each of said at least twometal lines; at least two cathode pads surrounding said contiguousmetallic interconnect; and an anode pad positioned in said center of thediode elements.
 22. The diode element of claim 21, wherein saidsubstrate comprises n doped silicon.
 23. The diode element of claim 22,wherein said n doped silicon substrate has a thickness ranging from0.075 mm to 0.275 mm.
 24. The diode element of claim 21, wherein an n+doped region and a p+-doped region are separated from an n+ layer by anactive region.
 25. The diode element of claim 21, wherein saidcontiguous metallic interconnect and said at least two metal linesdefine a fishbone pattern.
 26. The diode element of claim 25 wherein theat least two metal lines are p+ and are spaced from each other by a gap.27. The diode element of claim 27 wherein the gap between the at leasttwo p+ metal lines is in a range of 100 μm to 180 μm.
 28. The diodeelement of claim 21 wherein the contiguous metallic interconnect and atleast two cathode pads are separated by a gap in a range of 25 μm to 75μm.
 29. The diode element of claim 21, further comprising anantireflective coating layer.
 30. The diode element of claim 29, whereinsaid antireflective coating layer is a thin film material.
 31. The diodeelement of claim 30 wherein said thin film material is one of an oxide,a sulfide, a fluoride, a nitride, a selenide, or a metal.
 32. The diodeelement of claim 29 wherein said antireflective coating is a silicondioxide antireflective.
 33. A diode, having a center, comprising: asubstrate having a front side and a back side; at least two metal lineson said front side, wherein each of said metal lines has a first end anda second end; a contiguous metallic interconnect, distinct from the atleast two metal lines; at least two cathode pads surrounding saidcontiguous metallic interconnect; and an anode pad positioned in saidcenter of the diode elements, wherein said contiguous metallicinterconnect encircles said metal lines and said anode pad and whereinsaid contiguous metallic interconnect is in physical communication withat least one of the first end or second end of each of said at least twometal lines.
 34. The diode of claim 33, wherein said substrate comprisesn doped silicon.
 35. The diode element of claim 33, wherein an n+ dopedregion and a p+-doped region are separated from an n+ layer by an activeregion.
 36. The diode of claim 33, wherein said contiguous metallicinterconnect and said at least two metal lines define a fishbonepattern.
 37. The diode of claim 34 wherein the at least two metal linesare p+ and are spaced from each other by a gap.
 38. The diode of claim37 wherein the gap between the at least two p+ metal lines is in a rangeof 100 μm to 180 μm.
 39. The diode of claim 33 wherein the contiguousmetallic interconnect and at least two cathode pads are separated by agap in a range of 25 μm to 75 μm.
 40. The diode element of claim 21,further comprising an antireflective coating layer comprising at leastone an oxide, a sulfide, a fluoride, a nitride, a selenide, or a metal.